A) sWRX8 B) AM4 C) FP6 D) SP3
A) DDR5 and LPDDR5 B) DDR4-3200 in octa-channel mode C) Eight-channel DDR4-3200 D) DDR4-3200 in dual-channel mode
A) 64 KB (32 KB data + 32 KB instruction) B) 64 MiB C) 512 KB D) 32 KB
A) 64 KB B) 64 MiB C) 512 KB D) 32 KB
A) 24 B) 64 C) 16 D) 128
A) 8 B) 128 C) 16 D) 4
A) No integrated graphics B) Includes AV1 hardware decoding iGPU C) Includes dual GPUs D) Includes integrated GCN 5th generation GPU
A) TSMC 7FF B) GloFo 14 nm C) TSMC N7 FinFET D) TSMC N6
A) AM4 B) FP6 C) SP3 D) sWRX8
A) DDR5 and LPDDR5 B) DDR4-3200 in dual-channel mode C) Eight-channel DDR4-3200 D) DDR4-3200 in octa-channel mode
A) 8 B) 128 C) 24 D) 16
A) 4 B) 64 C) 16 D) 8
A) None B) AV1 hardware decoding GPU C) RDNA GPU D) GCN 5th generation GPU
A) FP6 B) SP3 C) sWRX8 D) AM4
A) DDR4-3200 in octa-channel mode B) DDR5 and LPDDR5 C) Eight-channel DDR4-3200 D) DDR4-3200 or LPDDR4-4266 in dual-channel mode
A) 16 B) 24 C) 128 D) 64
A) TSMC 7FF B) GloFo 14 nm C) TSMC N7 FinFET D) TSMC N6
A) Milan B) Barceló C) Rembrandt D) Cezanne
A) March 15, 2021 B) April 2022 C) November 2021 D) January 2020
A) sWRX8 socket B) FP6 socket C) AM4 socket D) SP3 socket
A) Zen 3+ microarchitecture B) Zen 2 microarchitecture C) Zen 4 microarchitecture D) Zen 3 microarchitecture
A) GloFo 14 nm process B) TSMC 7 nm process C) TSMC N7 FinFET D) TSMC N6 process
A) GloFo 14 nm process B) TSMC 7FF C) TSMC N6 process D) TSMC 7 nm process
A) Multiple B) One C) Eight D) Two
A) Eight-channel DDR4-3200 B) Octa-channel DDR4-3200 C) Dual-channel DDR4-3200 D) DDR5 and LPDDR5
A) 64 B) 128 C) 32 D) 8
A) GloFo 14 nm I/O die B) 64 MiB L3 cache dies (3D V-Cache) C) Integrated GCN GPU D) AV1 hardware decoding
A) Limited to uniprocessor operation (1P, single-socket) B) Limited to octa-channel memory only C) Limited to dual-processor operation (2P) D) Limited to 16 PCIe lanes
A) Zen 3+ B) Rembrandt C) Cezanne D) Milan
A) April 2022 B) January 2020 C) December 2022 D) March 15, 2021
A) 16 B) 30 C) 50 D) 128
A) Up to 50% B) Up to 64% C) Up to 10% D) Up to 30%
A) IPC is lower than Zen 3 B) IPC is 50% higher C) IPC is 30% higher D) IPC is identical to that of Zen 3
A) TSMC 7FF node B) TSMC N7 FinFET node C) TSMC N6 node D) GloFo 14 nm node
A) Barceló B) Rembrandt C) Milan D) Cezanne
A) 3D V-Cache decoding B) GCN 5th generation decoding C) AV1 hardware decoding D) USB4 decoding
A) November 5, 2020 B) April 1, 2022 C) Early 2017 D) April 20, 2022
A) Matisse B) Vermeer C) Raphael D) Milan
A) 600 series B) 100 series C) 500 series D) 300 series
A) 10% B) 25% C) 15% D) 19%
A) Integrated RDNA3 graphics B) Power efficiency and power management C) DDR5 memory controller and new sockets D) Larger L2 cache and higher core counts
A) 16MB B) 32MB C) 128MB D) 64MB
A) 4 B) 2 C) 1 D) 8
A) DirectStorage B) Resizable BAR C) 3D V-Cache D) Infinity Fabric
A) 46 clock cycles B) 32 clock cycles C) 39 clock cycles D) 12 clock cycles
A) 39 cycles B) 12 cycles C) 46 cycles D) 64 cycles
A) 512KB B) 16MB C) 64MB D) 32MB
A) 39 cycles B) 4 cycles C) 12 cycles D) 46 cycles
A) 64MB B) 32MB C) 96MB D) 128MB
A) Ryzen 9 5950X B) Ryzen 5 5600X3D C) Ryzen 6000 series D) Ryzen 7000X3D family
A) DDR3 B) DDR4 C) DDR5 D) HBM2
A) AM5 B) SP5 C) AM4 D) sTRX8
A) April 1, 2022 B) November 5, 2020 C) Early 2017 D) 2019
A) Two four-core complexes B) Single eight-core complex C) Four two-core complexes D) One single-core complex
A) 64MB B) 32MB C) 16MB D) 8MB
A) 16MB B) 8MB C) 64MB D) 32MB
A) 256 entries B) 1024 entries C) 2048 entries D) 512 entries
A) 32-bit Vector Arithmetic Execution System B) 256-bit Vector AES instructions C) 128-bit Variable Accelerated Execution Set D) 64-bit Virtual Advanced Encryption Standard
A) Integer vector processing B) Cache line invalidation C) Branch target prediction D) Broadcast TLB flushing
A) Central Encryption Transfer / Safe Storage B) Core Execution Thread / System Security C) Cache Enhancement Technology / Security State D) Control-flow Enforcement Technology / Shadow Stack
A) 96 B) 180 C) 92 D) 192
A) 96 B) 180 C) 92 D) 224
A) 96 entries B) 256 entries C) 192 entries D) 180 entries
A) 92 entries B) 192 entries C) 180 entries D) 224 entries
A) 256 B) 192 C) 96 D) 224
A) 92 B) 224 C) 256 D) 180
A) 4 B) 8 C) 10 D) 6
A) DDR4-2933 B) DDR4-2400 C) DDR4-2667 D) DDR4-3200
A) DDR4-2133 B) DDR4-2667 C) DDR4-2933 D) DDR4-3200
A) Raphael B) Vermeer C) Warhol D) Pinnacle Ridge
A) Mid-2021 B) Mid-2023 C) Mid-2020 D) Mid-2018
A) Raphael B) Vermeer C) Pinnacle Ridge D) Warhol
A) A full redesign B) A downgrade in core count C) A modest architectural refresh D) A brand new microarchitecture from scratch
A) Raphael B) Vermeer C) Warhol D) Pinnacle Ridge
A) It was delayed until 2024 B) It was released as Ryzen 5000 C) It was outsourced to Intel D) It was cancelled by AMD
A) Global chip shortage B) Raw material surplus C) Transportation strike D) Global energy crisis
A) Worldwide B) Only in Taiwan C) Exclusively in Europe D) Only in North America
A) Vega B) RDNA2 C) RDNA1 D) Navi
A) TR4, sTRX4 B) FP7, FP7r2 C) FP5, FP6 D) AM4, AM5
A) Rembrandt-X B) Rembrandt-R C) Rembrandt-Refresh D) Rembrandt-Plus
A) October 2025 B) November 2024 C) April 2022 D) January 2023 |