A) AM4 B) FP6 C) SP3 D) sWRX8
A) DDR5 and LPDDR5 B) DDR4-3200 in dual-channel mode C) Eight-channel DDR4-3200 D) DDR4-3200 in octa-channel mode
A) 32 KB B) 512 KB C) 64 KB (32 KB data + 32 KB instruction) D) 64 MiB
A) 64 MiB B) 512 KB C) 32 KB D) 64 KB
A) 24 B) 16 C) 64 D) 128
A) 8 B) 4 C) 128 D) 16
A) No integrated graphics B) Includes AV1 hardware decoding iGPU C) Includes dual GPUs D) Includes integrated GCN 5th generation GPU
A) TSMC N6 B) TSMC 7FF C) TSMC N7 FinFET D) GloFo 14 nm
A) FP6 B) sWRX8 C) SP3 D) AM4
A) DDR5 and LPDDR5 B) Eight-channel DDR4-3200 C) DDR4-3200 in octa-channel mode D) DDR4-3200 in dual-channel mode
A) 8 B) 24 C) 128 D) 16
A) 4 B) 16 C) 8 D) 64
A) RDNA GPU B) GCN 5th generation GPU C) AV1 hardware decoding GPU D) None
A) AM4 B) sWRX8 C) SP3 D) FP6
A) DDR5 and LPDDR5 B) DDR4-3200 or LPDDR4-4266 in dual-channel mode C) DDR4-3200 in octa-channel mode D) Eight-channel DDR4-3200
A) 16 B) 64 C) 24 D) 128
A) TSMC N7 FinFET B) TSMC 7FF C) GloFo 14 nm D) TSMC N6
A) Milan B) Cezanne C) Barceló D) Rembrandt
A) January 2020 B) April 2022 C) March 15, 2021 D) November 2021
A) AM4 socket B) SP3 socket C) sWRX8 socket D) FP6 socket
A) Zen 2 microarchitecture B) Zen 4 microarchitecture C) Zen 3 microarchitecture D) Zen 3+ microarchitecture
A) TSMC 7 nm process B) GloFo 14 nm process C) TSMC N7 FinFET D) TSMC N6 process
A) TSMC 7FF B) GloFo 14 nm process C) TSMC N6 process D) TSMC 7 nm process
A) Eight B) Two C) Multiple D) One
A) DDR5 and LPDDR5 B) Eight-channel DDR4-3200 C) Octa-channel DDR4-3200 D) Dual-channel DDR4-3200
A) 32 B) 128 C) 64 D) 8
A) 64 MiB L3 cache dies (3D V-Cache) B) AV1 hardware decoding C) GloFo 14 nm I/O die D) Integrated GCN GPU
A) Limited to octa-channel memory only B) Limited to uniprocessor operation (1P, single-socket) C) Limited to dual-processor operation (2P) D) Limited to 16 PCIe lanes
A) Cezanne B) Zen 3+ C) Milan D) Rembrandt
A) April 2022 B) March 15, 2021 C) January 2020 D) December 2022
A) 50 B) 30 C) 16 D) 128
A) Up to 30% B) Up to 10% C) Up to 64% D) Up to 50%
A) IPC is lower than Zen 3 B) IPC is 30% higher C) IPC is 50% higher D) IPC is identical to that of Zen 3
A) TSMC N6 node B) TSMC N7 FinFET node C) GloFo 14 nm node D) TSMC 7FF node
A) Rembrandt B) Barceló C) Milan D) Cezanne
A) GCN 5th generation decoding B) 3D V-Cache decoding C) AV1 hardware decoding D) USB4 decoding
A) Early 2017 B) April 20, 2022 C) April 1, 2022 D) November 5, 2020
A) Vermeer B) Raphael C) Milan D) Matisse
A) 300 series B) 600 series C) 100 series D) 500 series
A) 10% B) 19% C) 25% D) 15%
A) Power efficiency and power management B) DDR5 memory controller and new sockets C) Larger L2 cache and higher core counts D) Integrated RDNA3 graphics
A) 16MB B) 128MB C) 64MB D) 32MB
A) 1 B) 2 C) 4 D) 8
A) DirectStorage B) Resizable BAR C) 3D V-Cache D) Infinity Fabric
A) 12 clock cycles B) 32 clock cycles C) 39 clock cycles D) 46 clock cycles
A) 64 cycles B) 39 cycles C) 12 cycles D) 46 cycles
A) 16MB B) 64MB C) 512KB D) 32MB
A) 39 cycles B) 12 cycles C) 46 cycles D) 4 cycles
A) 64MB B) 128MB C) 32MB D) 96MB
A) Ryzen 9 5950X B) Ryzen 5 5600X3D C) Ryzen 6000 series D) Ryzen 7000X3D family
A) DDR3 B) DDR4 C) HBM2 D) DDR5
A) sTRX8 B) SP5 C) AM4 D) AM5
A) November 5, 2020 B) April 1, 2022 C) Early 2017 D) 2019
A) One single-core complex B) Two four-core complexes C) Single eight-core complex D) Four two-core complexes
A) 64MB B) 32MB C) 8MB D) 16MB
A) 8MB B) 16MB C) 64MB D) 32MB
A) 2048 entries B) 256 entries C) 512 entries D) 1024 entries
A) 256-bit Vector AES instructions B) 64-bit Virtual Advanced Encryption Standard C) 32-bit Vector Arithmetic Execution System D) 128-bit Variable Accelerated Execution Set
A) Broadcast TLB flushing B) Integer vector processing C) Cache line invalidation D) Branch target prediction
A) Control-flow Enforcement Technology / Shadow Stack B) Central Encryption Transfer / Safe Storage C) Cache Enhancement Technology / Security State D) Core Execution Thread / System Security
A) 92 B) 180 C) 192 D) 96
A) 224 B) 92 C) 96 D) 180
A) 96 entries B) 256 entries C) 180 entries D) 192 entries
A) 92 entries B) 180 entries C) 224 entries D) 192 entries
A) 96 B) 192 C) 224 D) 256
A) 224 B) 92 C) 256 D) 180
A) 10 B) 8 C) 4 D) 6
A) DDR4-3200 B) DDR4-2933 C) DDR4-2667 D) DDR4-2400
A) DDR4-2933 B) DDR4-3200 C) DDR4-2667 D) DDR4-2133
A) Vermeer B) Warhol C) Raphael D) Pinnacle Ridge
A) Mid-2018 B) Mid-2021 C) Mid-2023 D) Mid-2020
A) Vermeer B) Pinnacle Ridge C) Raphael D) Warhol
A) A modest architectural refresh B) A downgrade in core count C) A full redesign D) A brand new microarchitecture from scratch
A) Warhol B) Raphael C) Pinnacle Ridge D) Vermeer
A) It was outsourced to Intel B) It was released as Ryzen 5000 C) It was delayed until 2024 D) It was cancelled by AMD
A) Transportation strike B) Global chip shortage C) Raw material surplus D) Global energy crisis
A) Only in Taiwan B) Exclusively in Europe C) Only in North America D) Worldwide
A) RDNA1 B) RDNA2 C) Navi D) Vega
A) TR4, sTRX4 B) AM4, AM5 C) FP5, FP6 D) FP7, FP7r2
A) Rembrandt-Plus B) Rembrandt-R C) Rembrandt-X D) Rembrandt-Refresh
A) January 2023 B) November 2024 C) April 2022 D) October 2025 |